13 research outputs found

    POCS-based framework of signal reconstruction from generalized non-uniform samples

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    We formalize the use of projections onto convex sets (POCS) for the reconstruction of signals from non-uniform samples in their highest generality. This covers signals in any Hilbert space H\mathscr H, including multi-dimensional and multi-channel signals, and samples that are most generally inner products of the signals with given kernel functions in H\mathscr H. An attractive feature of the POCS method is the unconditional convergence of its iterates to an estimate that is consistent with the samples of the input, even when these samples are of very heterogeneous nature on top of their non-uniformity, and/or under insufficient sampling. Moreover, the error of the iterates is systematically monotonically decreasing, and their limit retrieves the input signal whenever the samples are uniquely characteristic of this signal. In the second part of the paper, we focus on the case where the sampling kernel functions are orthogonal in H\mathscr H, while the input may be confined in a smaller closed space A\mathscr A (of bandlimitation for example). This covers the increasingly popular application of time encoding by integration, including multi-channel encoding. We push the analysis of the POCS method in this case by giving a special parallelized version of it, showing its connection with the pseudo-inversion of the linear operator defined by the samples, and giving a multiplierless discrete-time implementation of it that paradoxically accelerates the convergence of the iteration.Comment: 12 pages, 4 figures, 1 tabl

    Unfairness of Random Access with Collision Avoidance in Industrial Internet of Things Networks

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    This paper is focused on the analysis of unfairness of random media access in Local Operating Networks (LON), which is one of the commercial platforms of the Industrial Internet of Things (IIoT). The unfairness in accessing the LON channel is introduced by a collision avoidance mechanism in the predictive p-persistent CSMA protocol adopted at the media access control layer. The study on the bandwidth share in predictive p-persistent CSMA calls for the analysis of multiple memoryless backoff. In this paper, it is shown that the channel access in LON systems is unfair in the short term for medium traffic load conditions, and in the long term for heavy loaded networks. Furthermore, it is explained that the average bandwidth allocated to a particular node is determined implicitly by the load scenario, while an actual node bandwidth fluctuates in time according to stochastic dynamics of the predictive p-persistent CSMA. Next, it is formally proven that the average bandwidth available to a node is a linear function of its backoff state and does not depend on backoff states of the other stations. Finally, it is demonstrated that possibly unfair bandwidth share in LON networks determined implicitly by load scenario is stable because, with lowering a fraction of actual network bandwidth accessible by a given station, the probability to decrease it in the future also drops

    www.mdpi.org/sensors Analysis of Mean Access Delay in Variable-Window CSMA

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    Abstract: The paper addresses the problem of the mean access delay characteristics in term of the channel load for networked sensor/control systems in LonWorks/EIA-709 technology. The system modelling is focused on the Media Access Control protocol that provides the load prediction and determines the key network characteristics. The network model assumes the consistency of load prediction between the nodes, and that the Transaction Control Sublayer does not introduce limitations on the data transmission. The latter means that the numbers of concurrent outgoing transactions being in progress are unlimited. Furthermore, it is assumed that the destination addresses of transmitted messages are distributed rather than concentrated on particular nodes. The analytical approach based on Markov chains is applied. The calculation of transition probabilities of the Markov chain is exemplified by the load scenario where all the transactions are acknowledged, unicast, and the optional collision detection is enabled. On the basis of the stochastic analysis, the probabilities of a successful transmission and collision, respectively, are computed. Furthermore, the numerical results of the mean access delay are reported. The simulative validation of analytical results is provided

    Problemy ekstremalne dla parabolicznych systemów nieskończonego rzędu z warunkami brzegowymi, w których występują całkowe opóźnienia czasowe

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    Extremal problems for integral time lag infinite order parabolic systems are studied in the paper. An optimal boundary control problem for distributed infinite order parabolic systems in which integral time lags appear in the Neumann boundary conditions is solved. Such equations constitute in a linear approximation a universal mathematical model for many diffusion processes (e.g., modeling and control of heat transfer processes). The time horizon is fixed. Using the Dubovicki-Milutin framework, the necessary and sufficient conditions of optimality for the Neumann problem with the quadratic performance indexes and constrained control are derived.Zaprezentowano ekstremalne problemy dla systemów parabolicznych nieskończonego rzędu z całkowymi opóźnieniami czasowymi. Rozwiązano problem optymalnego sterowania brzegowego dla systemów parabolicznych nieskończonego rzędu, w których całkowe opóźnienia czasowe występują w warunkach brzegowych Neumanna. Tego rodzaju równania stanowią w liniowym przybliżeniu uniwersalny model matematyczny dla procesów dyfuzyjnych. Korzystając z metody Dubowickiego-Milutina wyprowadzono warunki konieczne i wystarczające optymalności dla problemu liniowo-kwadratowego

    A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements

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    The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control

    Systematization and Comparison of the Binary Successive Approximation Variants

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    This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants

    Frequency-domain adaptive-resolution level-crossing-sampling ADC

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    EBCCSP 2017: 3rd International Conference on Event-Based Control, Communication and Signal Processing, Funchal, Madeira, Portugal, 24-26 May 2017In the framework of the large-scale wireless sensor networks involved in the Internet-of-Things (IoT), analog-to-digital converters (ADCs) must target ever increasing levels of power efficiency and amenability to ultra-scaled CMOS technologies. Digitally intensive architectures and smart conversion algorithms are therefore the fuel of future ultra-low power (ULP) designs. The minimization of the output average bitrate is an effective way to maximize the system energy efficiency. Level-crossing-sampling (LC) ADCs are a class of converters that addresses such problem. In their conventional implementation, however, they are mainly impaired by analog blocks (i.e. the high-performance comparators), difficult to be designed in deep nanoscale CMOS. This paper describes a highly-digital frequency-domain implementation of a LC ADC, which replaces the analog comparators with an oscillator-based quantizer and simple digital logic. LC is performed in the digital frequency-domain, where the application of adaptive-resolution algorithms to further enhance power efficiency becomes straightforward. Behavioral modeling simulations demonstrate the appropriateness of the proposed topology by comparing it with the conventional designs and by evaluating the impact of the oscillator-based-quantizer nonidealities on the ADC performance.European Commission Horizon 2020Science Foundation IrelandPolish National Center of Scienc
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